SCALABLE AND LOW POWER NETWORK ON CHIP DESIGN FOR RECONFIGURABLE SYSTEMS

Abstract

In the recent times reconfigurable systems have emerged as an alternative to the customized IC solutions. As a result the electronics industry is shifting towards using reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) as the computing platforms. Reconfigurable computing can also be viewed as a trade off between general purpose computing and application specific designs. Since reconfigurable systems provide the architecture and design flexibility, they have increased the progress in the hardware software co design technology and as a result finding applications in various areas such as scientific and biological computing, artificial intelligence, signal processing, security computing and control oriented design etc. As the number of components in reconfigurable systems increases, interconnecting all these components is becoming more and more challenging. Therefore, a more structured high level interconnect able to reduce the design effort and improve hardware efficiency is becoming necessity for these systems. To overcome theses interconnect challenges, various intra-chip communication techniques such as point to point and bus based systems were applied. But these techniques showed the lack of scalability. As a result, Network on Chip (NoC) has arisen as a more efficient and scalable solution to this problem. In a NoC-based system, packets are transmitted from a source to a destination PE (processing element) via routers (switches) arranged by links. The arrangement of interconnections between the PEs determines the topology of the NoC based system. The reconfigurable hardware solutions are based on computing architectures able to adapt their behaviour in response to several different inputs. Moreover, efforts are made to apply the reconfiguration techniques to all level of computing systems, for intrachip communication structures (buffers, topologies, memories, routers, etc.) as well as processor's micro architecture ( instruction set, data path, cache hierarchy etc.). Keeping in mind the above mentioned issues current thesis work has been carried out. A scalable and low power NoC for reconfigurable systems is designed in this thesis. Stress has been put in designing the reconfigurable and power efficient components of the NoC like routers and links. For this purpose Verilog hardware iii description language is used for the design entry and Modelsim 10.3 for simulation and Xilinx ISE design suit is used for the synthesis of routers and links. Spartan-6 FPGAs are used for the implementation of these routers and links. Topology selection has been done with the help of various performance metrics like maximum end-to- end latency, dropping probability and throughput etc. 2-D Mesh is found suitable for this work from these analyses. Four reconfigurable and power efficient routers namely Reconfigurable Router to Improve Efficiency (RRIE), Heterogeneous Reconfigurable Router for Low Power and High Performance (HRRLPHP), Eight Directional Reconfigurable Router for High Throughput (EDRRHT), Smart Reconfigurable Router for Online Detection of Faulty Blocks (SRRODFB) and three high performance, low power links namely High Speed Low Power Link for reconfigurable systems (HSLPL), Link to Minimize Switching Transitions for Reducing Dynamic Power for reconfigurable system (LMSTRDP and Link by Multi-encoding to Reduce Transition Activities in reconfigurable systems (LMRTA) have been designed and tested in the present thesis. The first designed router is RRIE which has a FIFO, channel flow/control logic and a crossbar as a switch. Compared to the earlier designed reconfigurable routers in the literature, this router has low area, consumes less power and provides high performance. It dissipates only around 15mW of power and occupies 64% smaller area compared to the earlier designed homogeneous routers. The problem with RRIE is that it does not support the heterogeneous data. This problem is removed in the second router HRRLPHP. To reduce the area further two tag bits have been added in this router which are able to indicate the direction of the output from the crossbar. The control circuitry of this router has been improved by including features like acknowledge for writing, acknowledge for reading, request and grant signals for writing in another channel's FIFO. The modified channels, FIFO and crossbar are designed and tested and it shows the significant improvement in area and power dissipation. Area of around 53 mm2 and power dissipation of only 0.020 w is estimated in this case. The drawback of this router is that the throughput is degraded marginally (3%). This drawback is removed in our third designed router namely EDRRHT. Also, semi-buffer concept is introduced in EDRRHT. Four more directions (NE, NW, SE & SW) are added so that router is now able to support eight directions. It also supports buffer-less storage concept to store the data of four newly added directions. Data of newly added directions share FIFOs with their neighbours to store the data. This way, this router requires less area for implementation. The newly iv designed architecture is able to provide more routes to the router for data routing. Thus it is helpful in decreasing critical path length and helps in increasing the performance. Also, rectilinear stennier tree path has been used to shorten the data path of the router. Furthermore, a circular FIFO is used in place of the normal fall-through FIFO. Although power dissipation of 0.045 w and area of 85 mm2 are slightly higher than the previous router, it is still better as compared to other routers in terms of other features and performance. In addition, a router which is able to recognize and differentiate between permanent and transient errors and the way to handle them and to handle the spotting of faulty blocks of a NoC is also designed in the present thesis. It is given the name SRRODFB and is a smart reconfigurable router for online detection of faulty blocks. It is also able to enhance the throughput, the network load and the data packet latency. In place of buffers, FIFO is used to achieve better performance. Hence it is able to have low area, low power dissipation and high performance compared to the other designed routers in this work as well in literature. In the proposed HSLPL link, MUX gating technique is used which is able to reduce the power dissipation as well as latency. In the second link namely LMSTRDP, we have reduced the number of transitions with the help of encoder and decoder. Power dissipation has been further reduced in this case. In the third link namely LMRTA, multi-coding technique has been used to reduce the transition activity. The rationale behind these proposed schemes for links is to minimize not only the switching activity but also coupling switching activity which is mainly responsible for link power dissipation.